This application is based on applications Nos. 10-284624, 10-286496, and 10-344137 filed in Japan, the contents of which are hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a data transmission/reception system, data reception device, and data transmission/reception method for synchronizing data transfer between the transmitter and the receiver.
2. Description of the Related Art
An image forming apparatus such as a digital copier (hereinafter xe2x80x9ccopierxe2x80x9d) performs image forming as follows: having a laser diode (LD) modulate based on image data read from a document to emit a laser beam, forming an electrostatic latent image on the surface of a photosensitive drum, developing the electrostatic latent image into a visible toner image with a developer, and transferring the toner image onto a transfer sheet.
In such an apparatus, data is transmitted/received between an image reading unit that reads the image data from the document and a printing unit that forms the electrostatic latent image by means of the LD modulation using the read image data.
For fast copying operations of the copier, the image data needs to be sent from the image reading unit to the printing unit at high speed. One method used for high-speed data transmission is a bit serial data transmission method.
In this method, the transmitter sends transmission data according to a predetermined clock signal (transmission clock signal), where the transmission data is made up of frames that each include a synchronization signal alternating between xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d bit-by-bit followed by information data of 8-bit strings representing textual or image information. The receiver receives the synchronization signal, generates a clock signal (reception clock signal) whose frequency and phase are equal to the synchronization signal, and samples the information data that follows using the reception clock signal.
For such data transmission/reception to be accurately performed, it is essential to match (synchronize) phases between the frequency of the transmission clock signal and the frequency of the reception clock signal. One example of synchronous methods is a PLL (Phase-Locked Loop).
FIG. 1 shows the general configuration of a PLL. In the figure, the PLL is roughly composed of a phase comparator 401, a lowpass filter (LPF) 402, and a voltage controlled oscillator (VCO) 403. The PLL has the VCO 403 generate a signal of a frequency in sync with a frequency (reference frequency 411) of an external input signal, in the following manner.
First, the phase comparator 401 compares an input comparison frequency 411 with the reference frequency 412 and outputs a signal 413 corresponding to a phase difference of the two frequencies to the LPF 402. The LPF 402 outputs a direct current component 414 obtained through the elimination of high frequency components from the signal 413 to the VCO 403. The VCO 403 is an oscillator whose output frequency varies with an input voltage, and outputs a signal of a frequency corresponding to a voltage of the direct current component 414. The signal outputted from the VCO 403 is then returned back to the phase comparator 401 with its frequency as the comparison frequency 412.
Alternatively, a frequency divider 404 may be inserted between the VCO 403 and the phase comparator 401. In this case, the comparison frequency 412 will be the result of frequency dividing the signal outputted from the VCO 403 by N (N is an integer no less than 1), so that the two signals will be synchronized where the VCO 403 oscillates at a frequency N times as large as the reference frequency 411.
As a result of repeating the above process of comparing the phase of the incoming reference frequency 411 with the phase of the comparison frequency 412 outputted from the VCO 403 and changing the input voltage of the VCO 403 based on the phase difference, the signal of the frequency (frequency N times as large as the reference frequency 411 if the frequency divider 404 is inserted) in sync with the reference frequency 411 is generated from the VCO 403.
Such PLLs are used in copiers to bring the frequency (equivalent of the comparison frequency 412) of the reception clock signal in the printing unit (receiver) into sync with the frequency (equivalent of the reference frequency 411) of the transmission clock signal outputted from the image reading unit (transmitter).
Synchronous processing in a copier has two main stages. The first synchronous processing is referred to as xe2x80x9csynchronous settingxe2x80x9d that is performed prior to copying operations, such as when the copier is powered up. In this stage the transmission clock signal and the reception clock signal are synchronized at a predetermined frequency (hereafter xe2x80x9csynchronization frequencyxe2x80x9d) in preparation for copying operations. The synchronization frequency is generally set according to the standard (voltage-frequency characteristic) of a VCO that generates the reception clock signal.
The second synchronous processing is referred to as xe2x80x9csynchronous adjustmentxe2x80x9d that is performed each time a copying operation is executed or each time copying operations for a predetermined volume are completed. The synchronous adjustment is to recover the reception clock frequency, that gradually deviates from the synchronization frequency due to leakage currents occurring in the PLL during standby or data transmission/reception, to be synchronous to the synchronization frequency.
Given increasing demands for faster image forming of copiers, transfer rates of image data directly affect the performance of the machine, so that it is desirable to minimize the time taken for the synchronous adjustment that is the preprocessing of the image data transfer. The synchronous adjustment time depends on the synchronization frequency which has been set during the synchronous setting.
FIG. 2 shows the voltage-frequency characteristic of the VCO. Although the VCO changes its output frequency relative to an input voltage, the PLL can perform synchronization only within a synchronous range shown by solid line 501. Besides, there is a property that synchronous processing takes more time when the synchronization frequency is around the upper limit Fa or lower limit Fb (point H or L) of the synchronous range, than when the synchronization frequency is around median frequency Fm (point M) of the synchronous range. This is because leakage currents increase as the synchronization frequency approximates to the upper or lower limit of the synchronous range, thereby causing a greater frequency deviation. It is therefore preferable to set the synchronization frequency at around point M (frequency Fm, input voltage Vm) in the synchronous range.
Accordingly, in the synchronous setting the image reading unit (transmitter) outputs a signal of frequency Fm at point M to the printing unit (receiver) as the transmission clock signal, and the printing unit activates the PLL with frequency Fm as the reference frequency (synchronization frequency) to synchronize the reception clock signal to the transmission clock signal.
Nevertheless, the frequency band of the VCO synchronous range varies with changes in solid state and use environment of the copier, so that the transmitter outputting a signal at a predetermined frequency (Fm in FIG. 2) does not necessarily mean the receiver synchronizing with the transmitter at the center (around point M) of the synchronous range. There may be cases where the synchronization frequency is set at a frequency band (e.g. around point H or L) which is undesirable for the synchronous adjustment.
Especially, the synchronous range becomes smaller if a VCO with a crystal of a narrower frequency variable range is used in order to stabilize transfer rates. To perform synchronization at the center of the synchronous range in such a case is even more difficult.
FIG. 3 shows a change of the synchronous range in the receiver""s VCO caused by the variation of use environment of the VCO. Solid line 501 shows the synchronous range before the change (same as FIG. 2), while solid line 601 shows the synchronous range after the change. The synchronous range has decreased in frequency in this example. Note here that according to the VCO characteristic the synchronous range varies in frequency with changes in solid state or use environment of the VCO but is stable in input voltage (Vaxcx9cVb in FIGS. 2 and 3) regardless of such changes.
Suppose the transmitter outputs a transmission clock signal of frequency Fm to the receiver so that synchronization be performed at point M, without knowing the synchronous range of the receiver""s VCO has changed. Then the transmission clock signal and the reception clock signal are synchronized at around point N which is close to the upper limit of the new synchronous range, instead of around point Mxe2x80x2 which is the center of the new synchronous range. Synchronous processing (synchronous adjustment) performed at point N takes more time than synchronous processing performed at point Mxe2x80x2, which results in a decrease in data transfer efficiency.
As mentioned above, the PLL is made up of a closed loop circuit including the VCO, the phase comparator, and the LPF. In the PLL the synchronization signal and the clock signal from the VCO are inputted into the phase comparator, which detects phase components (phase difference) of the two signals, converts the phase difference to a pulse signal (phase difference signal) and outputs the phase difference signal to the LPF.
The LPF is mainly composed of a resistor and a capacitor. The LPF removes unwanted noise components from the phase difference signal, converts the phase difference signal to a direct voltage, and outputs the voltage to the VCO. The VCO changes the phase of the clock signal to a direction such that the phase difference disappears, and outputs the clock signal to the phase comparator. By repeating this process, the phase of the clock signal approximates to the phase of the synchronization signal and eventually the two signals become in phase with each other (this process is called xe2x80x9cphase equalizationxe2x80x9d) Specifically, the phase equalization is performed so as to diminish the phase difference between the same-directional edges (rising edges) of the synchronization signal and the clock signal.
However, even if the clock signal is made in phase with the synchronization signal by the phase equalization, subsequent occurrence of leakage currents in the PLL causes gradual changes in frequency and phase of the clock signal over the course of time. Therefore, for accurate sampling of information data it is desirable to perform the phase equalization on each frame.
However, in the above bit serial data transmission method using the PLL that receives serial data via only a transmission line, there is a problem of low transmission rate due to inability to receive information data while receiving a synchronization signal. To improve the transfer efficiency in such a method, it may be considered appropriate to minimize the time for transmitting the synchronization signal. However, given that the PLL is made up of the closed loop circuit that reduces the phase difference by steering the frequency of the VCO relative to the phase difference, the larger the phase difference, the more time is necessary for the phase equalization. Accordingly, the transmission time of the synchronization signal has to be long enough for the phase equalization to be reliably executed even when the phase difference of the two signals is largest, that is, when the two signals is 180xc2x0 out of phase. Otherwise, the phase equalization may not be able to be completed during reception of the synchronization signal. When this happens, information data will be sampled using clock pulses of a frequency different from the synchronization signal and as a result accurate information data will not be obtained. This seriously undermines the communication reliability of the copier.
Such a problem is not limited to methods of generating clock signals using PLLs but can be present in any data reception device which generates a clock signal in phase with an incoming synchronization signal.
The asynchronous serial transmission method is a data transmission method whereby the system can be configured at low cost, since it requires only a transmission line.
In this method, the transmitter sends serial data in frames that are each made up of synchronization data including start bit data and effective data of 8-bit strings such as image gradation data and textual data, via the transmission line according to a transmission clock signal.
The receiver which receives the serial data is a conventional data reception device that is provided with a crystal oscillator. The receiver includes an oscillator for generating a reception clock signal which is similar to the transmission clock signal in frequency and is asynchronous to the transmission clock signal, a delay circuit for generating multiple delayed clock signals that are equal to the reception clock signal in frequency but differ with the reception clock signal in phase, and a phase detecting unit for selecting, based on the synchronization data, one of the delayed clock signals whose phase approximately matches the transmission clock signal in the first bit time of effective data of a frame. With this construction, it is possible to position a reading edge of the synchronization signal at around the center of the first bit time of the effective data. Accordingly, the data setup time and the data hold time can be made approximately equivalent. Assume the crystal oscillator has a normal error (plus or minus several tens of ppm). For effective data roughly corresponding to gradation data of a line read from a document by the image reading unit at 1400 dpi, sending this effective data in a frame will not cause failures of reading a level shown by each bit and so the effective data can be reliably latched.
However, in view of the recent trend of increasing amounts of data to be transferred per frame associated with denser document reading rates of such as 1600 dpi, even a slight error of the crystal oscillator will cause gradual deviation of each reading edge of the synchronization clock signal from the center of a bit time towards the phase advance direction or the phase delay direction, over the first bit time to last bit time of the effective data. In other words, if the amount of effective data in a frame is increased to meet the currently demanded level, the data setup time or the data hold time becomes shorter over time, which will eventually cause reception errors. Thus, with the conventional method the amount of data to be transferred per frame cannot be increased and so the data transfer efficiency remains low.
Though this problem may be solved by using a crystal oscillator whose error is smaller than the normal error, such a crystal oscillator is very expensive, so that manufacturing data reception devices with such crystal oscillators would be costly.
In view of the above problems, the present invention aims to improve the efficiency of the data transfer from the transmitter to the receiver.
The above object can be fulfilled by a data transmission/reception system that includes a transmission device for transmitting data according to a transmission clock signal and a reception device for receiving the data according to a reception clock signal, the transmission device including: a transmission clock signal generator which generates the transmission clock signal; a reception clock signal information receiver which receives information about the reception clock signal from the reception device; and a controller which controls a frequency of the transmission clock signal in accordance with the received information, and the reception device including: a reception clock signal generator which generates the reception clock signal in such a manner that the reception clock signal is synchronized to the transmission clock signal; and a reception clock signal information outputting unit which outputs the information about the reception clock signal when synchronization of the reception clock signal to the transmission clock signal is completed in the reception clock signal generator, to the transmission device.
With this construction, the transmission device receives the information about the reception clock signal which has been synchronized to the transmission clock signal from the reception device, and adjusts the frequency of the transmission clock signal based on the received information. Accordingly, time taken for synchronous processing in data transmission/reception is reduced, so that data can be transferred with efficiency.
Here, the information sent from the reception device to the transmission device may be an input voltage applied to a VCO in a PLL used in the reception device for synchronization between the two clock signals. Accordingly, the transmission device can optimally adjust the frequency of the transmission clock signal based on the notified input voltage.
The above object can also be fulfilled by a data reception device for receiving transmission data that includes synchronization data and effective data, the data reception device including: a clock pulse generator which generates a clock pulse; a selecting unit which detects phase differences between same-directional edges of the generated clock pulse and a transmission clock pulse included in the received synchronization data and between opposite-directional edges of the clock pulse and the transmission clock pulse, and selects a combination of edges whose phase difference is smallest among the detected phase differences; a phase adjusting circuit which adjusts a phase of the clock pulse to eliminate the phase difference of the selected combination of edges; and a sampling circuit which samples the effective data according to the clock pulse whose phase has been adjusted.
With this construction, the phase of the clock pulse generated in the data reception device is adjusted so as to eliminate the smallest phase difference among phase differences of the clock pulse and transmission clock pulse shown by the received synchronization data, on their same-directional edges and opposite-directional edges. In so doing, an amount of phase adjustment is reduced compared with the conventional method which concerns only the phase difference of the clock pulse and transmission clock pulse on their same-directional edges. Accordingly, time required for the phase adjustment is reduced, with it being possible to accelerate transmission of the synchronization data and so increase the data transfer efficiency.
The above object can also be fulfilled by a data reception device for receiving serial data including a plurality of frames which each include synchronization data and effective data, the data reception device including: a reception clock signal generator which generates a reception clock signal whose frequency is approximately equal to a frequency of a transmission clock signal, the reception clock signal being asynchronous to the transmission clock signal; a delayed clock signal outputting unit which outputs, in accordance with the synchronization data, a delayed clock signal whose phase approximately matches a phase of the transmission clock signal, the delayed clock signal being created by delaying a phase of the reception clock signal; an adjustment amount obtaining unit which obtains a phase adjustment amount according to a frequency difference of the reception clock signal with the transmission clock signal; and a setting unit which sets a synchronization clock signal for capturing effective data included in the frame, in accordance with the phase adjustment amount and the delayed clock signal.
With this construction, the data reception device selects the delayed clock signal which has been created by delaying the reception clock signal equal to the transmission clock signal in frequency and which approximately matches the phase of the transmission clock signal, and acquires the amount of phase adjustment based on the frequency difference of the reception clock signal with the transmission clock signal. The data reception device then determines the optimal synchronization clock signal with reference to the delayed clock signal and amount of phase adjustment. Accordingly, even when there is a certain frequency error between the transmission clock signal and the reception clock signal, a large amount of effective data can be reliably sampled without failing to read a level of each bit of the effective data. As a result, the amount of effective data in a frame can be increased, which contributes to an improvement in data transfer efficiency.